perf_user_access (arm64 and riscv only) Controls user space access for reading perf event counters.
for arm64 The default value is 0 (access disabled).
When set to 1, user space can read performance monitor counter registers directly.
See Perf for more information.
for riscv When set to 0, user space access is disabled.
The default value is 1, user space can read performance monitor counter registers through perf, any direct access without perf intervention will trigger an illegal instruction.
When set to 2, which enables legacy mode (user space has direct access to cycle and insret CSRs only). Note that this legacy value is deprecated and will be removed once all user space applications are fixed.
Note that the time CSR is always directly accessible to all modes.